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  <Article>
    <Journal>
      <PublisherName>ijesm</PublisherName>
      <JournalTitle>International Journal of Engineering, Science and</JournalTitle>
      <PISSN>I</PISSN>
      <EISSN>S</EISSN>
      <Volume-Issue>Volume 6, Issue 8,</Volume-Issue>
      <PartNumber/>
      <IssueTopic>Multidisciplinary</IssueTopic>
      <IssueLanguage>English</IssueLanguage>
      <Season>December 2017 (Special Issue)</Season>
      <SpecialIssue>N</SpecialIssue>
      <SupplementaryIssue>N</SupplementaryIssue>
      <IssueOA>Y</IssueOA>
      <PubDate>
        <Year>2017</Year>
        <Month>12</Month>
        <Day>24</Day>
      </PubDate>
      <ArticleType>Engineering, Science and Mathematics</ArticleType>
      <ArticleTitle>DESIGN OF HIGH SPEED LOW POWER PARALLEL ADDER USING BEC TECHNIQUE</ArticleTitle>
      <SubTitle/>
      <ArticleLanguage>English</ArticleLanguage>
      <ArticleOA>Y</ArticleOA>
      <FirstPage>856</FirstPage>
      <LastPage>868</LastPage>
      <AuthorList>
        <Author>
          <FirstName>Kala Priya.K*		 Rajani Chandra</FirstName>
          <LastName>CH**</LastName>
          <AuthorLanguage>English</AuthorLanguage>
          <Affiliation/>
          <CorrespondingAuthor>N</CorrespondingAuthor>
          <ORCID/>
        </Author>
      </AuthorList>
      <DOI/>
      <Abstract>Addition is a fundamental operation for any digital system, digital signal processing or control system. A fast and accurate operation of a digital system is greatly influenced by the performance of the resident adders.Adders are also very important component in digital systems because of their extensive use in other basic digital operations such as subtraction, multiplication and division. Hence, improving performance of the digital  adder  would  greatly  advance  the  execution  of  binary  operations  inside  a  circuit compromised of such blocks. The performance of a digital circuit block is gauged by analysingits power dissipation, layout area and its operating speed. As a result, the need for faster and efficient Adders in computers has been a topic of interest over decades.</Abstract>
      <AbstractLanguage>English</AbstractLanguage>
      <Keywords>Adders,Binary adders, Parallel-prefix adders, Verilog, Xilinx</Keywords>
      <URLs>
        <Abstract>https://ijesm.co.in/ubijournal-v1copy/journals/abstract.php?article_id=4316&amp;title=DESIGN OF HIGH SPEED LOW POWER PARALLEL ADDER USING BEC TECHNIQUE</Abstract>
      </URLs>
      <References>
        <ReferencesarticleTitle>References</ReferencesarticleTitle>
        <ReferencesfirstPage>16</ReferencesfirstPage>
        <ReferenceslastPage>19</ReferenceslastPage>
        <References/>
      </References>
    </Journal>
  </Article>
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