INTERNATIONAL JOURNAL OF ENGINEERING, SCIENCE AND - Volume 6, Issue 8,, December 2017 (Special Issue)

Pages: 856-868

Date of Publication: 24-Dec-2017

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DESIGN OF HIGH SPEED LOW POWER PARALLEL ADDER USING BEC TECHNIQUE

Author: Kala Priya.K* Rajani Chandra CH**

Category: Engineering, Science and Mathematics

Abstract:

Addition is a fundamental operation for any digital system, digital signal processing or control system. A fast and accurate operation of a digital system is greatly influenced by the performance of the resident adders.Adders are also very important component in digital systems because of their extensive use in other basic digital operations such as subtraction, multiplication and division. Hence, improving performance of the digital adder would greatly advance the execution of binary operations inside a circuit compromised of such blocks. The performance of a digital circuit block is gauged by analysingits power dissipation, layout area and its operating speed. As a result, the need for faster and efficient Adders in computers has been a topic of interest over decades.

Keywords: Adders, Binary adders, Parallel-prefix adders, Verilog, Xilinx