Date of Publication: 06-Jan-2013
AN AREA EFFICIENT ADDER DESIGN FOR VLSI CIRCUITS
Author: Lekshmi Devi V.S?
Category: Engineering, Science and Mathematics
In VLSI world, the design of area and power efficient high speed logic data paths has always been a hot topic of research. Carry Select Adder (CSLA) is one of the fastest adders used in many processors for performing fast arithmetic functions. The objective of the project is to develop a synthesizable CSLA model by making use of use of a simple and efficient gate-level modification. Modified design was compared for area, power and speed with the existing regular CSLA architecture.
Keywords: CSLA, Xilinx, BEC